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A Performance Analytical Strategy for Network-on-Chip Router with Input Buffer Architecture
  • ISSN号：1582-7445
  • 期刊名称：Advances in Electrical and Computer Engineering
  • 时间：2012
  • 页码：19-24
  • 相关项目：片上网络的通信性能-功耗联合建模与优化设计
作者： J. Wang|Y. Li|H. Li|
同期刊论文项目
片上网络的通信性能-功耗联合建模与优化设计
期刊论文 12 会议论文 2
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A Genetic Algorithm for Task Scheduling on NoC Using FDH Cross Efficiency
A Parallel Viterbi Algorithm for Low Latency TBCC Decoding.
A New CDMA Encoding/DecodingMethod for on Chip Communication Network
An Energy-efficient Scheduling Algorithm forComputation-Intensive Tasks on NoC-based MPSoCs
A System-level Bandwidth Design Method for Wormhole Network-on-Chip
A Performance Analytical Strategy for Network-on-ChipRouter with Input Buffer Architecture.
A List Simulated Annealing Algorithm for Task Scheduling on Network-on-Chip.