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中文摘要：
基于分布式RLC传输线,提出在互连延迟满足目标延迟的条件下,利用拉格朗日函数改变插入缓冲器数目与尺寸来减小互连功耗和面积的优化模型.在65nm CMOS工艺下,对两组不同类型的互连线进行计算比较,验证该模型在改善互连功耗与面积方面的优点.此模型更适合全局互连线的优化,而且互连线越长,优化效果越明显,能够应用于纳米级SOC的计算机辅助设计和集成电路优化设计.
英文摘要：
Repeater optimization is key for SOC interconnect delay design. This paper proposes a novel optimal model for minimizing power and area overhead of repeaters while meeting the target performance of on-chip interconnect lines. A Lagrangian function is presented to find the number of repeaters and their sizes required for minimizing area and power overhead with a target delay constraint. Based on 65nm CMOS technology, the computed results of the intermediate and global lines show that the proposed model can significantly reduce the area and power of interconnect lines and is especially suitable for global lines. The best performance will be achieved with the longer line. The proposed model can be integrated into repeater design methodology and CAD tools for interconnect planning in nanometer SOCs.
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