在下一代核心路由器的研究中.需要在规定的硬件成本和功耗限制下同时实现超高速路由表的查找和更新是目前研究的难点.论文提出了一个全新的超高速路由表查找及更新算法.该算法采用了基于索引和路由表隐式压缩的方案,不仅实现了可以在每一个SRAM的访问延时周期内输出一个路由查找结果.而且能够在两次SRAM的读写访问延时下完成路由更新.该算法功耗小,存储效率高,整个路由表的信息都可存放在容量接近于1M字节的SRAM中.
Internet protocol (IP) address lookup is a critical function of the network processors. While lots of solutions to this problem have been presented, few of them achieves line rate lookup and high update performance, high memory efficiency, and low hardware cost simultaneously. It is popular to use the content addressable memory devices for current commercial products, but it is a high cost, high power solution, particularly when applied to large databases. This paper presentes a novel high performance routing table lookup and update algorithm. According to the all-around performance, such as search and update performance, cost and consuming power, this work is better than the state-of-the-art. This algorithm is based on the index and compressed bit vector. Here not only one SRAM access cycle routing table lookup performance is accomplished but also two SRAM access cycles update performance is achieved in a pipelined scheme. The search and update proeess is illustrated in details. A maximum 530k routing entries can be held in about 1Mbytes SRAM space.