中文摘要：

A readout integrated circuit(ROIC) for a MEMS(microelectromechanical system)-array-based focal plane(MAFP) intended for imaging applications is presented.The ROIC incorporates current sources for diode detectors,scanners,timing sequence controllers,differential buffered injection-capacitive trans-impedance amplifier(DBI-CTIA) and 10-bit cyclic ADCs,and is integrated with MAFP using 3-D integration technology.A small-signal equivalent model is built to include thermal detectors into circuit simulations.The biasing current is optimized in terms of signal-to-noise ratio and power consumption.Layout design is tailored to fulfill the requirements of 3-D integration and to adapt to the size of MAFP elements,with not all but only the 2 bottom metal layers to complete nearly all the interconnections in DBI-CTIA and ADC in a 40 μm wide column.Experimental chips are designed and fabricated in a 0.35 μm CMOS mixed signal process,and verified in a code density test of which the results indicate a(0.29/-0.31) LSB differential nonlinearity(DNL) and a(0.61/-0.45) LSB integral nonlinearity(INL).Spectrum analysis shows that the effective number of bits(ENOB) is 9.09.The ROIC consumes 248 mW of power at most if not to cut off quiescent current paths when not needed.

英文摘要：

A readout integrated circuit （ROIC） for a MEMS （microelectromechanical system）-array-based focal plane （MAFP） intended for imaging applications is presented. The ROIC incorporates current sources for diode de- tectors, scanners, timing sequence controllers, differential buffered injection-capacitive trans-impedance amplifier （DBI-CTIA） and 10-bit cyclic ADCs, and is integrated with MAFP using 3-D integration technology. A small-signal equivalent model is built to include thermal detectors into circuit simulations. The biasing current is optimized in terms of signal-to-noise ratio and power consumption. Layout design is tailored to fulfill the requirements of 3-D integration and to adapt to the size of MAFP elements, with not all but only the 2 bottom metal layers to complete nearly all the interconnections in DBI-CTIA and ADC in a 40/zm wide column. Experimental chips are designed and fabricated in a 0.35 μm CMOS mixed signal process, and verified in a code density test of which the results indicate a （0.29/-0.31） LSB differential nonlinearity （DNL） and a （0.61/-0.45） LSB integral nonlinearity （INL）. Spectrum analysis shows that the effective number of bits （ENOB） is 9.09. The RO1C consumes 248 mW of power at most if not to cut off quiescent current paths when not needed.