中文摘要：

AES密码是目前主流应用的加密算法,研究了在面积优化的同时兼顾加密速度的解决方法。根据字节代换的要求和特点,S盒变换采用16×16位的空间预存储置换表,通过O（1）查表效率即可实现Sub Bytes变换。将伽罗华域上所有元素的两倍先存储在一张表格中,相应运算只需要通过查表和相加就可以完成,避免了有限域的乘法运算,有效减少了运算次数。密钥扩展是独立于加密算法本身的一个特殊模块,采用上升沿有效的时钟控制密钥生成方法,在生成密钥的同一个时钟周期下降沿进行密钥传递,减少了系统延时,增强了并行性,使得面积优化后的AES加密效率更高,吞吐量更大。通过计数器控制加密函数调用的轮数,使得每个模块能多次被调用,从而使得加密芯片面积减少。实验表明在Xilinx Virtex-5 FPGA上优化后的加密模块所占用面积为11 163 Slices,相比优化之前的20 173 Slices,占用面积减少了将近一半。

英文摘要：

AES is the mainstream encryption algorithm now. This paper studied that AES implementation had less area and high throughout rate. According to the characteristics of the substitution,S-box transformation used 16 × 16 pre-stored permutation table so that lookup efficiency space could be achieve O（ 1）. All the galois field elements 2 times were stored in a table the first. All of the computing needed only look-up table and addition. This was to avoid the finite field multiplication and effectively reduce the number of operations. Key expansion was independent of the encryption algorithm itself. It used positive edge of the clock to control key generation. It could send key at the falling edge of the same clock cycle. This could make the area optimized and achieve high throughput rate without waiting for the arrival of the next clock edge. It controlled the rounds of calling encryption function by counter. Each module could also be called multiple times so that the encryption chip area was reduced. Experiments show that the area of optimized AES occupies 11 163 Slices. It is decreased by 2 times compared to20 173 Slices of original AES.