探讨通过优化总线接口部件的设计来提高处理器整体性能,优化的措施着重于降低处理器访存的次数和减小总线负载。仿真和验证结果证明这些方法是可行有效的。
This paper discussed how to enhance the processor' s overall performance via optimize the design of the bus interface unit. The method is to reduce both the memory access times and the bus load, simulation and verification results show that the optimal method is feasible and effective.