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中文摘要：
论文提出了一种采用2维折线逼近的和积译码算法实现方案,避免了使用与量化比特数成指数关系增长的查找表,降低了译码器的存储器消耗。基于上述方案提出了一种次小值修正的最小和算法。该算法通过3个2维折线逼近对最小值进行修正,获得了逼近浮点和积算法的译码性能。算法的修正过程只包含简单的算术和逻辑运算,便于FPGA实现。
英文摘要：
An implementing scheme of sum-product algorithm is proposed based on 2-dimation broken line approach,which avoids the look-up table with size related to the exponential of the number of quantization bits and reduces the memory consumption of the decoder.Then,an algorithm called second-minimum value corrected min-sum algorithm is proposed based on the implementing scheme proposed above.The algorithm use three 2-dimension piecewise approach to correct the min-sum algorithm and its performance is very close to that of the floating point sum-product algorithm.The correction process of this algorithm just includes simple arithmetic and logic operations,which is easy to be implemented by FPGA.
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