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中文摘要：
设计了一个适合JPEG图像压缩系统的二维离散余弦变换模块，采用行列分离的方法，首先设计了一维余弦离散变换单元，该单元采用作者提出的改进的有符号分布式算法结构实现，在硬件实现上可以明显提高吞吐率，然后复用该单元完成二维离散余弦变换的FPGA设计，在所选器件EPF10KIOOEQC208-1综合后显示，一维余弦离散变换单元的最高频率可达到104．17MHz．满足JPEG图像压缩系统的高吞吐率要求.
英文摘要：
This paper designs two - dimensional discrete cosine transform module for the JPEG imagecompression system. The architecture of 2D - DCT is based on row - column decomposition method. The paper firstly designs a 1D - DCT unit based on distributed architecture improved by us, which can improve throughput clearly in hardware implementation, and then reuses the unit to complete the FPGA design of 2D - DCT. Synthesis and simulation results of 1D - DCT unit based on EPF10K100EQC208 - 1 show that the design clock is up to 104.17MHz and can meet JPEG image compression system.
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