中文摘要：

针对片上网络直径大、功耗高、可扩展性差以及物理实现复杂的问题,提出了一个低直径、且直径为常数的三维片上网络V-Mesh,并为该网络结构提供了VM路由算法.V-Mesh结构由一层2D Mesh子网和多层行/列互连子网通过三维堆叠技术互连而成,具有功耗低的特点,能支持任意多的节点数,可用于三维堆叠芯片中的节点间互连.相对于一种全互连3D片上网络F-Mesh来说,V-Mesh结构采用行/列互连技术大大减少了其长互连线条数,从而减少了功耗和布线复杂度,可扩展性强.理论分析和实验结果表明,和F-Mesh结构相比,V-Mesh结构的时延与其相当,但能够减少约12.5%的功耗开销.和3DMesh相比,在节点数较多的情况下,其时延能降低23%,吞吐量能提高12%,功耗能降低34%.总的来说,V-Mesh和3D Mesh相比各方面具有明显优势;和F-Mesh的互连性能相当,但其物理实现更为简单,布线量小,可扩展性更好.

英文摘要：

Aiming at these problems such as large diameter,inefficient energy,poor scalability,and complexity in physical implementation for Network-on-Chip,this paper puts forward a new3 D Network-on-Chip with the lower and constant diameter named V-Mesh and its routing algorithm called VM.The V-Mesh topology consists of a sub network with 2DMesh and multi-layer sub networks row/column interconnected,whose inter-layers are interconnected by 3Dstack technology.It has many advantages：efficient energy,ability to support any number of nodes.So it can be used to connect the nodes in the chips with 3Dstacked.Compared with a 3Dfullconnected network-on-chip named F-Mesh,the row/column-interconnected technology greatly reduces the number of lines in the V-Mesh structure,thus it can reduce the power consumption and layout complexity,and obtain a good scalability.Theoretic analyses and experiment results have shown the following conclusions：（1）compared with F-Mesh,the V-Mesh structure has similarlatency with 12.5% power consumption reduction;（2）compared with 3D Mesh,the V-Mesh structure can reduce latency by 23%and power consumption by 34%,and improve throughput by12%.In conclusion,V-Mesh has the interconnecting performance just like F-Mesh,but its physical implementation is much simpler than F-Mesh＇s,and it has less layout and better scalability too.V-Mesh has obvious advantages in various aspects than 3D Mesh also.