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中文摘要：
为了有效地提升异步零协议逻辑（NCL）流水线的吞吐量,该文提出一种多阈值并行完备流水线。采用独特的半静态零协议阈值门建立异步组合逻辑,使数据串行传输的同时每级流水线数据处理和完备检测并行进行,以串并结合的工作方式提升吞吐量。同时新阈值门的使用降低了流水线空周期时的静态功耗。基于SMIC 0.18μm标准CMOS工艺对所提出的流水线进行了分析测试。与现有流水线比较显示,当组合逻辑为四位串行进位全加器时,新的流水线吞吐量提升62.8%,静态功耗减少40.5%,可用于高速低功耗的异步电路设计。
英文摘要：
A multi-threshold pipeline based on parallel completion is proposed to improve the throughput of asynchronous NULL Convention Logic（NCL） pipeline.With the special semi-static NCL threshold gates to be realized asynchronous combinational logic,data processing and completion detection of each pipeline stage are carried out parallelly,meanwhile,the data get through the pipeline by using serial mode.The series-parallel ways improve the throughput of the pipeline.Moreover,the static power of the pipeline in NULL cycle declines as well because of the new threshold gates.The proposed pipeline is simulated based on SMIC 0.18 μm standard CMOS technology.Comparison results indicate that the throughput of the novel pipeline has an increment of 62.8% and the static power consumption is reduced by 40.5% with 4-bit NCL Ripper Adder serving as an asynchronous combinational logic.The proposed pipeline can be used to design high-speed low-power asynchronous circuit.
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An interconnecting bus power optimization method combining interconnect wire spacing with wire order
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