中文摘要：

针对多元低密度奇偶校验码（LDPC）译码器的资源消耗过大问题，设计了一种采用扩展最小和算法的低资源需求的多元LDPC译码器．采用以块为单位对信息进行迭代更新和Flooding传递调度策略的结构．为降低译码器的存储资源和逻辑资源，首先减小传递信息的深度，将变量节点更新和校验节点更新进行联合设计．同时，利用迭代时间差对变量节点更新和校验节点信息所需的资源进行复用．在具体实现中，对一个GF（64）域上码长为1044bit的非规则多元LDPC码，采用Xilinx公司XC4VLX60的现场可编程逻辑门阵列（FPGA）芯片设计了译码器．与现有文献相比，所提出的译码器结构可节约54％的存储资源和逻辑资源，且提高了译码速度和吞吐量．

英文摘要：

Due to the high resources demand during the decoding process of non-binary LDPC codes, a nonbinary LDPC decoder based on the EMS （ Extended Min-Sum） algorithm is proposed. The messages are updated iteratively in the block unit, and the flooding schedule is utilized in this proposed decoder. To reduce the storage resources and logical resources, the messages are first contracted in length. Then, the resources are multiplexed between the process of check nodes updating and that of variable nodes updating by the time difference. An FPGA chip for decoding an irregular non-binary LDPC over GF（64） of length 1 044 bit has been developed based on the Xilinx XCAVLX60 FPGA device. Compared to the existing solutions, about 54% storage resources and logical resources can be saved. Meanwhile, the decoding speed and throughput can be greatly improved.