中文摘要：

为加快锁相环的启动速度,文中提出了一种初始化电路,启动完成后,初始化电路停止工作,几乎不增加功耗.采用饱和输出鉴相鉴频器,扩展了鉴相鉴频器的工作范围.采用逻辑电路直接控制标准计数器并在脉冲分频器中消除吞咽计数器,节省了一个计数器,降低了功耗.采用0.18μm1.8V1P6MN阱标准CMOS数字工艺完成设计,版图面积为0.08mm^2.仿真结果表明,初始化电路和饱和输出鉴相鉴频器使得锁定时间减小了19%.在输出信号的频率为266MHz时,相对抖动峰-峰值小于2.5%,整个锁相环的功耗约为17mW.

英文摘要：

In order to speed up the startup of phase-locked loop（PLL）,an initialization circuit is proposed,which stops working after the startup has been finished and consumes little power.Then,a phase-frequency detctor（PFD） with saturated output is proposed to extend the working range of PFD.Moreover,a logic circuit is applied to directly control a standard counter and to simplify the pulse-swallow frequency divider into a single loop,thus saving a counter without increasing the power consumption.Finally,the standard CMOS logic process of 0. 18 μm 1.8 V 1P6M N trap is applied to the design with a layout area of 0. 08mm^2. Simulated results show that the application of both the initial circuit and the PFD with saturated output results in a decrease of locking time by 19% , and that, at a frequency of 266 MHz, the relative peak-peak jitter of the output signal is less than 2.5% and the total power consumption of the PLL is about 17 mW.