中文摘要：

为改善航空设备中时钟源抖动性能,针对时钟源产生电路——数字锁相环,提出了一种理论分析方法。该理论分析方法基于数字锁相环的Z域模型,通过逆Z变换,推导出数字锁相环内噪声在时间域上的响应公式。在响应公式的帮助下,分析数字锁相环环路参数对输出时钟抖动性能的影响,进而为设计高性能数字锁相环提供指导。为验证该理论分析方法,本文利用MATLAB语言搭建了数字锁相环的行为级模型。仿真结果表明,该方法可以明显改善数字锁相环的抖动性能。

英文摘要：

To improve the performance of the clock source in avionics, a theoretic analysis method is pro- posed to focuse on the clock source generator, digital phase-locked loop （DPLL）. Based on the DPLL z- domain model, the theoretic analysis deduces the time-domain response formulas of the noises in DPLL. With the help of the response formulas, the effects of DPLL loop parameters on the jitter performance are analyzed to guide the DPLL design. To verify the theoretic analysis, a DPLL behavior model is de- veloped in MATLAB. The simulation results show that the jitter performance of DPLL with the opti- mum filter parameters is improved significantly.