中文摘要：

本文提出了一个具有自调谐,自适应功能的1.9GHz的分数/整数锁相环频率综合器.该频率综合器采用模拟调谐和数字调谐相结合的技术来提高相位噪声性能.自适应环路被用来实现带宽自动调整,可以缩短环路的建立时间.通过打开或者关断ΣΔ调制器的输出来实现分数和整数分频两种工作模式,仅用一个可编程计数器实现吞脉冲分频器的功能.采用偏置滤波技术以及差分电感,在片压控振荡器具有很低的相位噪声;通过采用开关电容阵列,该压控振荡器可以工作在1.7GHz～2.1GHz的调谐范围.该频率综合器采用0.18μm,1.8V SMIC CMOS工艺实现.SpectreVerilog仿真表明：该频率综合器的环路带宽约为100kHz,在600kHz处的相位噪声优于-123dBc/Hz,具有小于15μs的锁定时间.

英文摘要：

A self-tuning, adaptive 1. 9GHz fractional-N/integer PLL based frequency synthesizer is proposed in the paper. A combined tuning technique of digital tuning and analog tuning is used to improve the phase noise of frequency synthesizer by decreasing the gain of VCO. The adaptive loop is introduced for automatic adjustment of the loop bandwidth, which can quicken the locking process. Two operation modes （integer/fractional-N） are achieved by switching on/off the output signal of ΣΑ modulator. Just a programmable counter is needed for the swallow pulse divider. The on-chip VCO achieves a low phase noise by utilizing a bias filter technique and a differential inductor, and a 1.7GHz 2.1GHz tuning range by a switched capacitor array. Based on 0.181xm 1.8V SMIC CMOS technology, SpectreVerilog simulation shows that the frequency synthesizer has a 100 kHz loop bandwidth, a 〈 151μs settling time, and the phase noise is lower than -123dBc at 600kHz offset.