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单密勒电容补偿的三级误差运放电路
  • 期刊名称：半导体学报,2007,28(10):1636-1641
  • 时间：0
  • 分类：TN43[电子电信—微电子学与固体电子学]
  • 作者机构：[1]电子科技大学电子薄膜与集成器件国家重点实验室,成都610054
  • 相关基金：国家自然科学基金重点资助项目（批准号：60436030）
  • 相关项目：单片功率系统集成（PSoC）的基础理论和技术研究
关键词： 单密勒电容, 低压三级运放, 双极零补偿法, single Miller capacitor, three-stage amplifier with low voltage, DPZC
中文摘要：

提出了一种新的单密勒电容补偿的低压三级误差运放结构和一种新的零极点补偿方法（DPZC），其利用两个前馈通路产生两个左半平面的零点去补偿运放主通路中的主极点及两个非主极点.运放传输函数的极点位置由运放主通路的参数决定，零点的位置由两个前馈通路的参数决定，因此改变运放零点的位置并不影响极点的位置，从而可以非常方便地控制补偿因子来获得所需的性能.仿真结果表明：本文提出的结构及补偿方法打破了传统的电路结构及补偿方法对运放带宽的限制，运放不仅具有非常大的带宽而且具有非常好的相位裕度.当负载为100pF//25kΩ，补偿电容为2pF及补偿因子为4时，该运放具有100dB的电压增益、25MHz的带宽、90°的相位裕度和0.625mW的功耗.

英文摘要：

An improved three-stage amplifier topology with a new frequency compensation technique is proposed. It can produce two left-half-plane zeros to compensate the two non-dominant poles and the dominant pole by adjusting the compensation factor,giving the amplifier very large bandwidth and good phase margin. Moreover,the amplifier requires only one small compensation capacitor and does not consume much power when driving a large load capacitor. A GBW of 25MHz,DC gain of 100dB,PM of 90° ,and power dissipation of 0. 625mW can be achieved for a load capacitor of 100pF with a single Miller compensation capacitance of 2pF and a compensation factor of 4 in 0. 5μm CMOS technology.

同期刊论文项目
单片功率系统集成（PSoC）的基础理论和技术研究
期刊论文 90
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