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Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor

ISSN号：1000-9000
期刊名称：《计算机科学技术学报：英文版》
时间：0
分类：TP368.1[自动化与计算机技术—计算机系统结构;自动化与计算机技术—计算机科学与技术]
作者机构：[1]Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences Beijing 100190, China, [2]Graduate University of Chinese Academy of Sciences, Beijing 100049, China
相关基金：This paper is supported in part by the National Natural Science Foundation of China under Grant Nos. 60633060, 60606008, 60776031, 60803031 and 90607010, and in part by the National Basic Research 973 Program of China under Grant Nos. 2005CB321604 and 2005CB321605, and in part by the National High Technology Research and Development 863 Program of China under Grant Nos. 2007AA01Z107, 2007AA01Z113, and 2007AA01Z476. Acknowledgement The authors thank Dr. Rui Li, and Marc Letreguilly from STMicroelectronics for providing sample testing results.

关键词：微处理器, 易测性, 设计, 测试性能, microprocessor design-for-testability, test generation, built-in self-test, at-speed testing

中文摘要：

这篇论文描述 design-for-testability (DFT ) 特征和一个通用微处理器的便宜测试答案。优化 DFT 特征详细被介绍。混合扫描压缩结构被执行并且完成压缩比超过十次。存储器内建的自我测试(BIST ) 电路与扫描领子被设计而不是位图减少区域开销并且改进测试并且调试效率。实现的 DFT 框架也利用了内部锁阶段的环(PLL ) 提供复杂在速度测试钟序列。因为仍然在这个 DFT 图案有限制，为这个盒子的测试策略是相当复杂的，与复杂自动测试模式产生(ATPG ) 并且调试流动。测试结果的样品在纸被给。在纸讨论的所有 DFT 方法是为大量的生产的原型(HVM ) DFT 计划象慢测试电源消费和费用一样实现高质量的测试目标。这篇文章的联机版本(做 i：10.1007/s11390-008-9193-0 ) 包含增补材料，它对授权用户可得到。

英文摘要：

This paper describes the design-for-testability （DFT） features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved compression ratio more than ten times. Memory built-in self-test （BIST） circuitries were designed with scan collars instead of bitmaps to reduce area overheads and to improve test and debug efficiency. The implemented DFT framework also utilized internal phase-locked loops （PLL） to provide complex at-speed test clock sequences. Since there are still limitations in this DFT design, the test strategies for this case are quite complex, with complicated automatic test pattern generation （ATPG） and debugging flow. The sample testing results are given in the paper. All the DFT methods discussed in the paper are prototypes for a high-volume manufacturing （HVM） DFT plan to meet high quality test goals as well as slow test power consumption and cost.

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