在空间应用和核辐射环境中,单粒子翻转(SEU)效应严重影响SRAM的可靠性。采用错误检测与校正(EDAC)和版图设计加固技术研究和设计了一款抗辐射SRAM芯片,以提高SRAM的抗单粒子翻转效应能力。内置的EDAC模块不仅实现了对存储数据“纠一检二”的功能,其附加的存储数据错误标志位还简化了SRAM的测试方案。通过SRAM原型芯片的流片和测试,验证了EDAC电路的功能。与三模冗余技术相比,所设计的抗辐射SRAM芯片具有面积小、集成度高以及低功耗等优点。
The reliability of SRAM used in the environment of space and nuclear radiation is seriously decreased by SEU (Single Event Upset). In this paper, a radiation hardened SRAM proto type chip is researched and designed using EDAC (Error Detection and Correction) technol- ogy to improve the SRAM's tolerance to SEU effect. For the SRAM embedded with the EDAC function, one bit error in stored data can be corrected and two or more bit errors can be detected, moreover, the test program of SRAM is also simplified by storing data error flags in EDAC. The functions and electrical properties of SRAM with EDAC are verified by proto type chip test. Compared with the SRAM with TMR (Triple Modular Redundancy) technology, the SRAM de- signed in this paper has some advantages such as small area, high integration and low power.