中文摘要：

为了应对现代SOC复杂的时钟结构给跨时钟域信号处理带来的隐患，分析了跨时钟域信号产生的亚稳态现象的根本原因和常用的跨时钟域信号的处理方法，针对跨时钟域信号处理难以验证的问题，提出了基于随机延时注入的跨时钟域仿真验证方法．通过将亚稳态现象抽象成采样数据在时钟上的随机抖动，使得芯片设计的RTL前仿真在没有时钟树物理信息的情况下能够模拟出亚稳态效应．分析结果表明此方法能够完成SOC芯片的跨时钟域信号的功能验证．

英文摘要：

Complicated clock infer-structure of modem SO（2 brings potential problems related with CDC signal interface operations. The root cause of metastability caused by CDC and the methods dealing with it are discussed in detail. A random delay injection based CDC verification method is presented to meet the verification challenge of CDC. This method converts metastability into sample data random jitter lasting for one clock period, which makes it feasible the RTL pre-simulation when physical clock tree information is not available. The result of an example shows the method is suitable to do CDC verification for SOC designs.