中文摘要：

提出了一种数字分频器，根据分频器外部输入的分频比和占空比控制参数，对源时钟实现任意偶数、奇数和半整数分频，占空比全范围可调，包含50％。电路由VerilogHDL编程实现，并通过Xilinx公司SPARTANXC3S250E芯片硬件验证。测试表明该分频器结构简单功能稳定，资源占用不足1％，使用灵活，具有较强的可移植性。

英文摘要：

A digital frequency divider is proposed in this paper. According to the input division ratio and duty-cycle, the frequency divider can divide the source clock, no matter the division ratio is even, odd or half-integer. The duty-cycle is controllable in the whole range, including 50%. The cir- cuit, based on Verilog HDL, has passed the hardware verification with SPARTAN XC3S250E of Xilinx. The simulation results show that the divider is simple and stable, and it only occupies less than 1% of the FPGA resources. It is flexible and has strong transplantation.