中文摘要：

通过介绍C＋＋语言配合VerilogHDL来进行数字逻辑设计的模式,提出了一种由C＋＋到Verilog来实现逻辑设计的崭新方法此方法从系统设计（虚拟机）入手,用C＋＋来搭建所需要的系统模型,再由Verilog与C＋＋的一致性转化,将软件设计精确地转化到硬件级上,使得逻辑设计向上可进行软硬件的联合仿真,向下能够实现物理级延伸通过该方法可有效地避免SOC设计中从系统到物理实现在转化过程中产生的逻辑不一致在简叙C＋＋的语言特性后,将Verilog与C＋＋进行了对比分析,给出了两种语言之间进行转化设计的实现方式结合数字信号处理器的设计,对此方法进行了设计应用,最终通过比对C＋＋与Verilog两者的仿真数据文件,对两种层次系统描述进行了测试验证

英文摘要：

A mode for designing the digital logic circuit through C ＋＋ language matching withVerilog HDL was introduced. Base on this,a brand-new method of designing logic circuit from C ＋＋ toVerilog was presented. This method starts from the system design （ virtual machine） and used C ＋＋ tobuild the required system model. Then,the software design is accurately translated into a hardware levelby Verilog and C ＋＋ consistency. So the logical design upwards can undertake joint simulation by software and hardware,and downwards can realize physical level outspread. This method can effectively avoid logic inconsistency when the SOC design is translated from system design to physical design. Some contrastive analyses about the difference of two languages were given after some language characteristics of C ＋＋ were formulated. Then translation way was given between C ＋＋ and Verilog HDL. Besides,the example of DSP designing was provided which can perform application of this method directly. Finally,the system description was verified by comparing the simulation data of C ＋＋ and Verilog.