中文摘要：

随着加密算法在嵌入式可信计算领域的广泛应用,如何提高其执行效率成为研究的热点问题.高级加密标准（AES）凭借其在安全性、费用开销和可执行性等方面的内在优势,成为使用最为广泛的对称密钥加密算法.采用指令集架构（ISA）扩展优化的方法对AES算法进行指令扩展优化.基于电子系统级（ESL）方法设计流程,使用基于LISA语言的处理器生成工具构建了一个高效AES专用指令处理器（AES_ASIP）模型,最终实现于FPGA中.经过一系列的仿真和验证,对比ARM处理器指令集架构,实验结果显示AES_ASIP以增加少许硬件资源为代价,提高了算法58.4x%的执行效率并节省了47.4x%的指令代码存储空间.

英文摘要：

Abstract Encryption algorithm has been used widely in the embedded trusted computing domain, so how to improve its execution efficiency has become an important issue. The Advanced Encryption Standard （AES） is a new encryption algorithm which has been widely adopted in the field of trust computation due to its high security, low cost and high enforceability. This paper employs a new instruction set architecture （ISA） extension method to optimize this algorithm. Based on the electronic system level （ESL） methodology, a commercial processor tool on the basis of language for instruction-set architectures （LISA） is used to construct an efficient AES application specific instruction processor （AES_ ASIP） with the objective tO improve the AES algorithm execution efficiency. Finally the AES_ASIP model is implemented in the FPGA （field-programmable gate array） platform. A series of simulations have been conducted to evaluate the performance of the AES_ASIP model. Experimental results show that our processor improves 58.4x% in the execution efficiency and saves 47.4x% in the code storage space compared with the ARM ISA processor.