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中文摘要：
为使计算机与ARINC429总线设备之间的数据通信更加方便,同时最大可能地降低设计成本.设计了ARINC429总线协议IP核,协议处理模块功能可以由可编程逻辑器件FPGA通过逻辑设计来实现,从而将总线的协议处理模块均集成于FPGA芯片上.在开发总线协议IP核时采用功能模块化方法,将逻辑设计划分为数据协议处理模块、缓冲模块、定时模块等部分.最后通过仿真验证,结果表明429总线协议IP核能够实现多通道数据的收发,逻辑设计符合ARINC429总线的数据传输要求,且满足特定场合的应用.
英文摘要：
In order to make the data communication between the computer and ARINC429 bus devices more easy and fast, and lessen the designing cost as low as possible, based on FPGA this article designs the ARINC429 bus protocol IP core. Protocol processing module was achieved by logic design in one FPGA chip. The integrated design and the operational principle of the IP core are given. With modular method, this design integrates the data protocol processing module, the data buffer module and timing module. Through simulation testing at last, the ARINC429 protocol IP core can achieve data transmission in multichannel and could meet the need of ARINC429 protocol character, and could be applied in series of situation.
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