中文摘要：

这份报纸基于并发的双乐队的数字 pre 弄歪(DPD ) 建议便宜硬件体系结构。体系结构被实现在上回答可编程的门数组(FPGA ) 补偿并发的双乐队的力量放大器(PA ) 的非线性。也就是，这实现介绍一种新奇模型复杂性减小技术进系统为分享的 out-of-band 查找表格(LUT ) 的时间部门 multiplexing。表演用宽带 class-F PA 与试验性的测试安装被评估。双乐队的信号中心频率由 80 MHz 分开了。更低、上面的中心频率分别地在 2.61 GHz 和 2.69 GHz 被定位。这新奇 DPD 实现维持优秀性能，但是使用 29.17% 与常规途径相比减少的硬件资源。邻近的隧道力量比率(ACPR ) 是的结果表演不到 59 dBc 和规范的均方差(NMSE ) 为上面的边带(USB ) 在为更低的边带(LSB ) 和 63dB 的 62dB 附近。

英文摘要：

This paper proposes a low-cost hardware architecture based on concurrent dual-band digital pre-distorter （DPD）. The architecture is implemented on field programmable gate array （FPGA） to compensate for the nonlinearity of the concurrent dual-band power amplifier （PA）. This implementation introduces a novel model complexity reduction technique into system, namely, time-division multiplexing for out-of-band lookup tables （LUTs） sharing. Performances are evaluated with an experimental test setup using a wideband class-F PA. The dual-band signal center frequency separated by 80 MHz. Lower and upper center frequency are located at 2.61 GHz and 2.69 GHz, respectively. This novel DPD implementation maintains excellent performance, but uses hardware resources reduced by 29.17% compared with conventional approaches. The results show that the adjacent channel power ratio （ACPR） is less than -59 dBc and normalized mean square error （NMSE） is around - 62dB for lower sideband （LSB） and - 63dB for upper sideband （USB）.