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中文摘要：
基于65nm CMOS工艺，综合考虑电容耦合与电感耦合效应，提出了一种互连线耦合串扰分布式RLC解析模型．采用函数逼近理论与降阶技术，在斜阶跃输入信号下，提出了被干扰线远端的串扰数值表达式．基于65nm CMOS工艺，对不同的互连耦合尺寸下的分布式RLC串扰解析模型和Hspice仿真结果进行了比较，误差绝对值都在2．50％内，能应用于纳米级SOC的计算机辅助设计．
英文摘要：
Based on the 65nm CMOS process,a novel parallel RLC coupling interconnect analytical model is presented synthetically considering parasitical capacitive and parasitical inductive effects. Applying function approximation and model order-reduction to the model, we derive a closed-form and time-domain waveform for the far-end crosstalk of a victim line under ramp input transition. For various interconnect coupling sizes, the proposed RLC coupling analytical model enables the estimation of the crosstalk voltage within 2.50% error compared with Hspice simulation in a 65nm CMOS process. This model can be used in computer-aided-design of nanometer SOCs.
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An interconnecting bus power optimization method combining interconnect wire spacing with wire order
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