中文摘要：

在电路设计的早期阶段，成品率与可靠性的关系模型对于预测和改善电路的成品率和可靠性具有极为重要的意义。结合广义门电路的版图结构与拓扑结构信息，分析了其缺陷密度及成品率和可靠性的损失机理，并构建了考虑缺陷生长特性的广义门电路成品率与可靠性损失概率之间的解析关系模型。基于该模型，又考虑到电路拓扑结构对故障的屏蔽效应，利用迭代的概率转移矩阵方法给出了门级电路成品率与可靠性之间的量化关系。理论分析与通过在 ISCAS85基准电路上采用经验公式和惯用方法的证明策略，验证了本文所提方法的合理性和有效性。还分析了工艺参数、老化因素等对电路成品率与可靠性关系的影响。

英文摘要：

Research on the relation between yield and reliability is obviously important for predicting and improving yield and reliability during the early production stage .Combining the layout structure and topological structure information of generalized gates ,analyzing the defect density ,the mechanism of yield and reliability loss ,then the loss probability models of yield and reliabili-ty of generalized gates were proposed ,and its relational expression was derived ,in which the growth characteristics of defect with time was considered .For the shielding effects in topological structure of circuit ,the quantitative relations between yield and reliabili-ty were given by the method of iterative probability transfer matrix based on the above models .Theoretical analysis and experimental results with ISCAS85 benchmark circuits show that the proposed model is reasonable .The impacts of process parameters ,burn-in on the relation between yield and reliability of circuit are analyzed .