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中文摘要：
针对IC前端设计中的关键技术，即将寄存器传输级（RTL）描述的手工综合成门级网表，通过人工参与的方式，运用数字电路设计知识将行为级代码用一些最基本的逻辑门（比如与非门、非门、或非门等）按照对应的综合电路模型得出其相应的门级电路。在ASIC设计过程中运用这种方法，不仅优化电路的结构，且能保证逻辑功能的正确性，同时可降低传输过程中的延迟，提高芯片设计的可靠性。因此，研究ASCI设计中的手工综合具有重要的实用价值。
英文摘要：
With the development of ASIC design rapidly,it is key technology of the front- end IC design that the register transfer level description is manually synthesized the register transfer level. Through artificial participation, behave - level code by some of the most basic logic gates（such as nand- door,non- door,nor-door,etc. ） gets the corresponding gate-level circuit according to the corresponding synthesized circuit model. Such methods used in ASIC design not only can optimize the circuit structure, but also can guarantee the correct logic function. At the same time,it can reduce the transmission delay and improve the reliability of chip design. Therefore,research on the ASCI design by manual synthesis is of practical value.
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