中文摘要：

多标准已成为视频编解码器的发展趋势，这给系统设计带来了性能和灵活性双重的挑战．根据视频标准间算法的异同点，提出并实现了一种多标准视频编解码器芯片的体系结构，支持包括H．264／AVC，AVS和VC-1的多个标准．系统级采用了基于宏块的多核流水线结构，在保持可编程性的基础上显著提高了系统级的并行度．模块级进行了详细的软硬划分设计，可配置的专用数据通路用以加速各模块的特定运算．VLSI实现表明，芯片面积仅为961kgate，且能保证NTSC（30fps）和PAL（25fps）的实时编解码．

英文摘要：

Supporting multi-standard is becoming the trend of video codec, which brings the challenge of both performance and flexibility in system design. The authors introduce the VLSI implementation of a video codec architecture which can support multiple video coding standards, including H. 264/ AVC, AVS, and VC-1. Algorithm characteristics of these standards are first analyzed. Based on the algorithm similarities and differences of them, several techniques are efficiently adopted to optimize the architecture at system level and module level. At system level, a four-stage macroblock-based pipeline consists Of five programmable cores, and all modules of the encoder and decoder are carefully mapped onto the pipeline architecture. The pipelined multi-core architecture can largely improve system performance by exploiting system level parallelism while maintaining the programmability. And at module level, dedicated data paths are efficiently embedded in the programmable cores to speed up the signal processing. Detailed module level HW/SW partition is proposed according to certain computation in each module. The implementation results show that the codec can guarantee real-time encoding or decoding NTSC （30fps）/PAL （25fps） videos in the worst case, using only 961kgate.