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背栅效应对SOI横向高压器件击穿特性的影响
  • 期刊名称：物理学报, 2007, 56(7):3990-3995
  • 时间：0
  • 分类：TN386[电子电信—物理电子学]
  • 作者机构：[1]电子科技大学微电子与固体电子学院,成都610054
  • 相关基金：国家自然科学基金重点项目（批准号：60436030）和模拟集成电路国家重点实验室（批准号：9140C0903010604）资助的课题.
  • 相关项目：单片功率系统集成（PSoC）的基础理论和技术研究
关键词： SOI, 背栅, 体内场降低, LDMOS, SOI, back-gate, reduced BULk field, LDMOS
中文摘要：

提出一种SOI基背栅体内场降低BG REBULF（back-gate reduced BULk field）耐压技术．其机理是背栅电压诱生界面电荷，调制有源区电场分布，降低体内漏端电场，提高体内源端电场，从而突破习用结构的纵向耐压限制，提高器件的击穿电压．借助二维数值仿真，分析背栅效应对厚膜高压SOI LDMOS（〉600V）击穿特性的影响，在背栅电压为330V时。实现器件击穿电压1020V，较习用结构提高47．83％．该技术的提出，为600V以上级SOI基高压功率器件和高压集成电路的实现提供了一种新的设计思路．

英文摘要：

A novel hack-gate reduced bulk field concept which makes a breakthrough in improving the vertical breakdown voltage ot high voltage SOI transistors is proposed. The mechanism of the improved breakdown characteristics is that the electric field distributions of the active region are modulated by the interface charges induced by the hack-gate voltage. The bulk electric field at the drain side is reduced, the bulk electric field at the source side is increased, and the breakdown voltage of the high voltage SOI device is improved. The impact of the hack-gate bias on thick film SOI LDMOS （over 600 V） is discussed via twodimensional simulations. When the back-gate bias is 330V, the breakdown voltage of the three-zone SOI double RESURF LDMOS is 1020V, which is 47.83 % greater than that of a conventional LDMOS. The novel eoncept presents a new method for realizing over 600 V high voltage power device and high voltage integrated circuit.

同期刊论文项目
单片功率系统集成（PSoC）的基础理论和技术研究
期刊论文 90
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