位置：成果数据库 > 期刊 > 期刊详情页
A RESURF Enhanced p-Channel Trench SOI LDMOS With Ultralow Specific ON-Resistance
  • ISSN号：0018-9383
  • 期刊名称：IEEE Transactions on Electron Devices
  • 时间：2014.7
  • 页码：2466-2472
  • 相关项目：高压、超低功耗的易集成SOI功率器件机理与新结构研究
作者： Xiaorong Luo|Q Xu|Zhaoji Li|Bo Zhang|
同期刊论文项目
高压、超低功耗的易集成SOI功率器件机理与新结构研究
期刊论文 37 会议论文 4 获奖 6
同项目期刊论文
A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration
A new analytical model for the surface electric field distribution and breakdown voltage of the SOI
Dual-gate lateral double-diffused metal-oxide semiconductor with ultra-low specific on-resistance
A Low Specific on-Resistance SOI Trench MOSFET with a Non-Depleted Embedded p-Island
A High Figure-of-Merit SOI MOSFET with a Double-Sided Charge Oxide-Trench
High-voltage super-junction lateral double-diffused metal oxide semiconductor with a partial lightly
A high voltage silicon-on-insulator lateral insulated gate bipolar transistor with a reduced cell-pi
A low on-resistance SOI LDMOS using a trench gate and a recessed drain
Ultralow specific on-resistance superjunction vertical DMOS with high-k dielectric pillar
Ultra-low specific on-resistance vertical double-diffused metal - Oxide semiconductor with a high-k
Ultra-low specific on-resistance vertical double-diffused metal-oxide semiconductor with a high-k di
Novel Low-Resistance Current Path UMOS With High-K Dielectric Pillars
Experimental and theoretical study of an improved breakdown voltage SOI LDMOSwith a reduced cell pit
Low specific on-resistance power MOSFET with a surface improved super-junction layer
An L-shaped low on-resistance current path SOI LDMOS with dielectric fieldenhancement
复合沟道氟离子增强型AlGaN/GaN HEMT的研究
A high voltage Bi-CMOS compatible buffer super-junction LDMOS with an N-typeburied layer
A low specific on-resistance SOI MOSFET with dual gates and recessed drain
A novel high figure-of-merit SOI SJ LDMOS with ultra-strong charge accumulation effect
Ultralow specific on-resistance high voltage trench SOI LDMOS with enhanced RESURF effect
Analytical Model and New Structure of the Variable- k Dielectric Trench VDMOS With Improved Breakdow
Novel Reduced ON-Resistance LDMOS With an Enhanced Breakdown Voltage
Low on-resistance high-voltage lateral double-diffused metal oxide semiconductor with a buried impro
A low on-resistance buried current path SOI p-channel LDMOS compatible with n-channel LDMOS
High voltage SOI LDMOS with a compound buried layer
Universal trench design method for a high-voltage SOI trench LDMOS
高k介质电导增强SOI LDMOS机理与优化设计
A high voltage Bi-CMOS compatible buffer super-junction LDMOS with an N-type buried layer
Eliminating the floating-body effects in a novel CMOS-compatible thin-SOI LDMOS
Analytical model for high-voltage SOI device with composite-k dielectric buried layer
Experimental and theoretical study of an improved breakdown voltage SOI LDMOS with a reduced cell pitch＊