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中文摘要：
为了减少测试应用时间并保证高测试数据压缩率，提出一种选择序列的并行折叠计数器。在分析并行折叠计算理论的基础上，通过记录表示折叠索引的组序号和组内序号生成选择状态的测试序列，避免了无用和冗余的测试序列的生成。ISCAS标准电路的实验结果表明，该方案的平均测试数据压缩率为94．48％，平均测试应用时间为类似方案的15．31％。
英文摘要：
In order to reduce the test application time and guarantee high test data compression rate, a selection sequence of parallel folding counter was proposed. Selection test sequences were generated by recording group number and in-group number which represented folding index based on the analysis of parallel folding computing theory, so as to avoid generating useless and redundant test sequences. The experimental results on ISCAS benchmark circuits demonstrate the average test compression rate of the proposed scheme is 94.48%, and the average test application time is 15.31% of the similar scheme.
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