中文摘要：

随着集成电路规模的不断扩大和器件特征尺寸的不断缩减，保持和改善集成电路的制造成品率成为优化电路设计和制造工艺研究的热点。为了减少由冗余物缺陷和丢失物缺陷所引起的成品率损失，选择优先优化的线网成为版图优化过程中的一个重要课题。基于关键面积减小的版图优化是提高集成电路成品率的一种有效途径。本文提出了一种新的短路、开路灵敏度模型，该模型以线网为单位，反映了单位线网上该线网与周围线网间的短路关键面积和自身开路关键面积的大小。由于本文的灵敏度模型是关于单一线网的，同时又包含候选线网周围线网的信息，因此，在优化时可以同时减少候选线网与周围线网之间的短路关键面积以及线网本身的开路关键面积，提高了版图优化的效率。实验结果表明，该灵敏度模型可作为版图优化中线网位置选择的依据。

英文摘要：

To maintain and improve the manufacturing yield of integrated circuit becomes a research hot spot in optimized circuit design and manufacturing technology, with the expansion of the integrated circuit scale and shrinkage of devices feature sizes. In order to reduce the yield loss caused by redundancy material defect and missing material defect, choosing a preferentially optimizing net becomes an important subject in the process of layout optimization. Layout optimization is an effective way to increase integrated circuit yield which is based on the critical area diminution. In the paper presented is a new kind of short circuit and open circuit sensitivity model, which is net-based and not only reflects the size of the short critical area between the single net and the nets around it, but also possesses open critical area. Because this model is based on single net and includes the information about the surrounding net, the short critical area between the single net and the net around it and the open critical area of its own can be reduced at the same time. In this way, the efficiency of layout optimization is enhanced. According to the experimental results, this sensitivity model can be used to choose the position for optimization.