中文摘要：

为了加快数控锁相环的锁定速度，该文提出了一种适用于数控锁相环的动态带宽调整算法以加快锁定速度。仅当鉴相器鉴出的3次相位差均小于一定边界条件时，该算法才减少数控锁相环的带宽，并当鉴出的相位差超出一定边界条件时，该算法将立即增加带宽。为验证所提出的动态带宽调整算法，该文在MATLAB环境中建立了数控锁相环行为级模型。仿真结果表明，在相同参数情况下，采用该文提出的动态带宽调整算法可使锁定时间缩短至采用传统动态带宽调整技术锁定时间的28.6%-85.7%。最后，该文采用CSM 0.18 μm 1P6M CMOS工艺实现数控锁相环并进行实测。实测结果表明，采用该文提出的动态带宽调整算法可快速消除相位差，并使得锁相环始终维持在相位锁定状态。该文提出的动态带宽调整算法，可以有效避免基于相位差调整锁相环频率的局限性，降低错误调整带宽的几率，继而加快锁定速度。

英文摘要：

To accelerate the locking speed of the Digitally Controlled Phase-Locked Loop （DCPLL）, a Dynamic Bandwidth Management （DBM） algorithm for DCPLL is presented. Only when the phase error sensed by the phase detector is less than the boundary condition for three times, the proposed algorithm decreases the DCPLL bandwidth. In addition, the proposed algorithm increases the DCPLL bandwidth immediately when the sensed phase error is larger the boundary condition. To verify the proposed algorithm, a behavioral model is developed in MATLAB environment. The simulation results show that, under the same condition, the locking time of the DCPLL with the proposed algorithm is reduced to 28.6%？85.7% of the locking time with the traditional DBM algorithm. Finally, a DCPLL is implemented by CSM 0.18 μm 1P6M CMOS and tested. The measured results show that the proposed algorithm can decrease the phase error rapidly and keep the DCPLL in locking status. Therefore, the proposed algorithm can avoid the limitation of traditional DBM algorithm, decrease the probability of changing the PLL bandwidth falsely, and accelerate the locking speed.