中文摘要：

本文在线阵CCD时序分析的基础上,以FPGA为主控芯片,利用Verilog硬件描述语言,设计了线阵CCD驱动电路和ADC接口时序逻辑控制电路,实现了以10帧/秒的速率采集3648个像素点,并将数据通过USB2.0接口上传至上位机保存、显示等功能,可为类似需求的CCD数据采集系统提供一种可供借鉴的技术参考。

英文摘要：

Based on the line array CCD timing analysis,a linear CCD driving circuit and ADC interface timing logic control circuit are designed by using FPGA based control chip and verilog hardware description language,collection of 3648 pixel at a rate of 10 frames per second is accomplished and data through USB2. 0 interface can be uploaded to the PC for saving,displaying and others,this paper provides a technical reference for CCD data acquisition system with similar requirement.