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DOIND： a technique for leakage reduction in nanoscale domino logic circuits
  • ISSN号：1674-4926
  • 期刊名称：《半导体学报：英文版》
  • 时间：0
  • 分类：TN791[电子电信—电路与系统] TN305.7[电子电信—物理电子学]
  • 作者机构：[1]Electronics & Telecommunication Engineering Department, IET-Devi Ahilya University, Indore-452017, India, [2]Electrical Engineering Department, Indian Institute of Technology, Bombay-400076, India
  • 相关基金：Project supported by the Strategic Priority Research Program of the Chinese Academy of Sciences（No.XDA09020402）; the National Key Basic Research Program of China（Nos.2013CBA01900,2010CB934300,2011CBA00607,2011CB932804）; the National Integrate Circuit Research Program of China（No.2009ZX02023-003）; the National Natural Science Foundation of China（No.61176122,61106001,61261160500,61376006）; the Science and Technology Council of Shanghai（Nos.12nm0503701,13DZ2295700,12QA1403900,13ZR1447200,14ZR1447500）
作者： Ambika Prasad Shah, Vaibhav Neema, Shreeniwas Daulatabad
关键词： 逻辑电路, 技术节点, 多米诺, 纳米级, 渗漏, 仿真结果, EDA工具, 逻辑方法, deep submicron, DOIND logic, domino logic, evaluation, precharge, subthreshold leakage
中文摘要：

A novel DOIND logic approach is proposed for domino logic, which reduces the leakage current with a minimum delay penalty. Simulation is performed at 70 nm technology node with supply voltage 1V for domino logic and DOIND logic based AND, OR, XOR and Half Adder circuits using the tanner EDA tool. Simulation results show that the proposed DOIND approach decreases the average leakage current by 68.83%, 66.6%, 77.86% and 74.34% for 2 input AND, OR, XOR and Half Adder respectively. The proposed approach also has 47.76% improvement in PDAP for the buffer circuit as compared to domino logic.

英文摘要：

A novel DOIND logic approach is proposed for domino logic, which reduces the leakage current with a minimum delay penalty. Simulation is performed at 70 nm technology node with supply voltage 1V for domino logic and DOIND logic based AND, OR, XOR and Half Adder circuits using the tanner EDA tool. Simulation results show that the proposed DOIND approach decreases the average leakage current by 68.83%, 66.6%, 77.86% and 74.34% for 2 input AND, OR, XOR and Half Adder respectively. The proposed approach also has 47.76% improvement in PDAP for the buffer circuit as compared to domino logic.

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期刊信息
  • 《半导体学报：英文版》
  • 中国科技核心期刊
  • 主管单位:中国科学院
  • 主办单位:中国电子学会 中国科学院半导体研究所
  • 主编：李树深
  • 地址：北京912信箱
  • 邮编：100083
  • 邮箱：cjs@semi.ac.cn
  • 电话：010-82304277
  • 国际标准刊号：ISSN：1674-4926
  • 国内统一刊号：ISSN：11-5781/TN
  • 邮发代号:2-184
  • 获奖情况:
  • 90年获中科院优秀期刊二等奖,92年获国家科委、中共中央宣传部和国家新闻出版署...,97年国家科委、中共中央中宣传部和国家新出版署三等奖,中国期刊方阵“双效”期刊
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  • 俄罗斯文摘杂志,美国化学文摘（网络版）,荷兰文摘与引文数据库,美国工程索引,美国剑桥科学文摘,英国科学文摘数据库,日本日本科学技术振兴机构数据库,中国中国科技核心期刊,中国北大核心期刊（2004版）,中国北大核心期刊（2008版）,英国英国皇家化学学会文摘,中国北大核心期刊（2000版）
  • 被引量:7754