中文摘要：

针对基于FPGA／ASIC的全数字硬件化实现时存在内部参数界确定以及字长选取等问题，通过分析离散周期对全数字硬件化实现的影响机理，得到离散周期对全数字硬件化系统的稳定性以及动态性能指标的影响规律。建立角度解算单元的连续域模型，并对稳定性进行分析；利用del—ta算子进行离散化，对比分析了有无反馈滞后一拍的离散角度解算单元的稳定性，得到包含离散周期信息的系数取值范围；以衰减度为满意控制指标，求得了满足性能指标的最大离散周期。分析结果表明，全数字硬件化实现全闭环数字算法时所存在的反馈滞后一拍会使KT〈2，从而使实际系统的稳定性降低。通过求取最大离散周期，能够平衡系统性能与数字实现代价之间的矛盾关系，为控制器参数设计提供理论依据。实验结果验证了理论分析的正确性。

英文摘要：

There are some problems such as determination of parameters-region and optimization of word- length etc. in all-digital full-hardware（ADFH） process based on field-programmable gate array（FPGA）/ application specific integrated circuits （ASIC）. By analyzing the effect of discrete period on ADFH, the influence law of discrete period on the stability and dynamic performance of ADFH was obtained. The sta- bility analysis of continuous system was done firstly, and then, the delta operator was employed to dis- crete the continuous-time system. The comparative stability analysis of discrete-time system with and without one-step-delay was conducted, and the parameters-region with discrete period was derived. The maximum period of discrete-time system was calculated using satisfactory control in which the desired per- formance index of decay rate was met. One-step-delay can make KpT less than 2 and reduce the stability. The maximum discrete period can balance the performance and cost of implementation. The simulation and experimental results verify the correctness and effectiveness of proposed method.