欢迎您！东篱公司
退出
-
申报数据库
-
立项数据库
-
成果数据库
-
项目获奖数据库
中文摘要：
设计了应用于GMSK调制，工作在2．4GHz，CMOS全差分的∑-△频率综合器．调制器中采用预补偿的分数N锁相环，推导了Ⅱ型三阶锁相环的传输函数，并指出影响环路传输函数的重要参数．介绍了校准重要的环路参数的方法，锁相环设计中采用差分调节的LC压控振荡器和全差分的电荷泵．设计的电路利用0．18μm 1P6M CMOS工艺进行仿真．由于锁相环的组成模块中采用了低功耗设计，锁相环的功耗仅为11mW左右，调制器的数据率达到2Mb／s．
英文摘要：
A CMOS fully-differential 2.4GHz ∑-△ frequency synthesizer for Gaussian minimum shift keying （GMSK）modulation is presented. A pre-compensation fractional-N phase-locked loop（PLL）is adopted in the modulator.The transfer function of the type- Ⅱ third-order phase-locked loop is deduced,and the important parameters that affect the loop transfer function are pointed out. Methods to calibrate the important loop parameters arc introduced. A differential tuned LC-VCO and a fully-differential charge pump are adopted in the PLL design. The designed circuits are simulated in a 0.18gm 1P6M CMOS process. The power consumption of the PLL is only about llmW with the low power consideration in building blocks design, and the data rate of the modulator can reach 2Mb/s.
同期刊论文项目
同项目期刊论文
期刊信息
位置：