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中文摘要：
介绍了高层次综合与布图规划相结合的基本方法与技术及其研究进展．该方法主要解决集成电路制造工艺的持续发展给集成电路电路设计所带来的2个问题：集成电路本身的集成复杂度使得集成电路的设计工作必须向更高的抽象层次前进；集成电路特征尺寸的缩小导致物理寄生效应已经在电路的时延、功耗等指标上成为主导因素，这要求在更高的抽象层次关注物理参数的影响．对本领域有代表性的算法进行了系统的描述，并且对这些算法的基本思路进行了分析和总结．
英文摘要：
The research on ＂integrating high level synthesis and floorplan＂ is a very important part in the research on electronic design automation. In this paper, the current research status of this field is introduced, and the basic methodologies and algorithms are also presented. These methodologies and algorithms are mainly focused on the following two problems, which are caused by the rapid development of IC fabrication technology. Firstly, with the fast increasing of the complexity of IC chips, it is necessary to start a design at a higher abstraction level. Secondly, as the feature size of IC keeps on shrinking into the nanometer level, physical effects have been playing a dominant role in final delay and power consumption of a circuit. In this paper, the typical algorithms of the 90 s of last century are described, and the basic principles of these algorithms are also analyzed and summarized.
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