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中文摘要：
针对处理器的数据通路中的通路时延故障，提出一种基于指令集的处理器时延测试产生方法．对于每条指令提取出状态矩阵，并基于状态矩阵将通路分为功能不可测（FUPs）和潜在功能可测的（PFTPs）．对PFTPs记录潜在测试指令（序列）组合，提取控制和数据约束，在门级进行有约束的非强健时延测试产生．最后的测试指令由控制指令（序列）＋潜在测试指令（序列）＋观测指令（序列）构成．
英文摘要：
An instruction-based path delay test generation method for the datapath of a processor is proposed, which apply the processor＇s own instructions in normal operation mode to test itself. Dataflowstate matrix is extracted for each instruction, based on the matrix, paths are classified into functional untestable paths （FUPs） and potential functional testable paths （PFTPs）. The potential test instructions for PFTPs are stored and the control and data constraints are extracted. Constrained combinational non-robust delay test pattern generation is applied. The final test instructions are composed of controllability instruction （s）, potential test instruction（s） and observability instruction（s）. The instruction set architecture, register transfer level （RTL） description along with gate level netlist are used in the approach. Experimental results indicate that a significant percentage of functional untestable paths are recognized in early stage and the control and data constraints do a great deal to help generating the test vectors that can be mapped into test instructions for PFTPs. Experimental results also show that the proposed method takes a much shorter CPU time than the earlier work.
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