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中文摘要：
为了满足高速运算应用的需要，给出了基于改进自适应时延估计算法的硬件设计与实现方案；首先根据单芯片硬件实现自适应时延估计的特点对该算法的操作顺序进行了调整并说明了其可行性；然后根据给出的系统框图，采用了基于流水线操作和并行结构的设计方法、定点纯小数的数据格式和适中字长以及层次化和模块化的方法，实现了算法的设计；计算机仿真结果表明，基于调整后算法的硬件实现的时延估计结果同原算法一样均收敛于理论值，因而设计与实现的方案是可行有效的。
英文摘要：
Aiming at the applications at high speed, a design and implementation of the LMSTDE algorithm based on FPGA is presented. The paper firstly develops to give the improvement to the LMSTDE algorithm based on the algorithm＇s implementation on a single chip of FPGA. Then the overall diagram of the improved algorithm＇s implementation is presented. Based on the diagram, the improved algorithm＇s implementation on FPGA is carried out with pipeline design and parallel structure, fixed-point decimal fraction data format and hiberarehy ＆ module methods. Finally, the simulation is carried out. The simulation result shows that the time delay of the improved LMSTDE algorithm converges at the true value as the original LMSTDE algorithm. The design and implementation presented is feasible and effective.
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