中文摘要：

在各类高清视频解码过程中,分像素插值是计算最为密集的处理环节之一.针对已有分像素插值结构在兼顾性能与灵活性方面所存在的不足,提出一种适用于多标准视频解码处理的可重构分像素插值结构设计.通过分析不同标准的插值计算模式之间的共性与差异,提出一种新型可重构并串混合滤波结构,其中的数据传输通路、输入/输出数据模式以及滤波计算单元均可进行动态配置,能够支持包括VC-1,H.264/263,AVS和MPEG-1/2/4在内的多种视频标准.实验结果表明,该设计能够完成多标准实时HDTV 1080 p（1920x1088@30 fps）视频解码;同已有工作相比,该设计在同等硅片资源下能够支持更多高清视频编解码标准.该设计目前已实际应用在一款多媒体SoC芯片中.

英文摘要：

Subpixel interpolation is one of the most computation-intensive parts in various HD video decoding processes.The existing subpixel interpolation architectures have difficulties in achieving high performance and flexibility simultaneously.This paper presents a reconfigurable sub-pixel interpolation architecture for multi-standard video decoding.Based on the analysis and comparison of commonalities and differences among interpolation algorithms of various standards,a novel reconfigurable parallel-serial-mixed filtering architecture is proposed,which allows dynamical configuration of the data transfer path,the I/O data pattern and the filter computation unit.It supports various video coding standards including VC-1,H.264/263,AVS and MPEG-1/2/4.The experimental results show that this design can achieve the real-time multi-standard HDTV 1080p（1920x1088@30 fps） video decoding.Compared to previous work,the proposed design can support more types of HD video coding standards while consuming the same amount of silicon resources.It has been applied in a multimedia SoC chip.