Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology
- ISSN号:1000-9000
- 期刊名称:《计算机科学技术学报:英文版》
- 时间:0
- 分类:TP368.1[自动化与计算机技术—计算机系统结构;自动化与计算机技术—计算机科学与技术]
- 作者机构:[1]Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences Beijing 100080, China, [2]ST Microelectronics, 39 Chemin du Camp-des-Filles, 1228 Plan Les Ouates, Geneva, Switzerland
- 相关基金:Supported by the National Natural Science Foundation of China for Distinguished Young Scholars under Grant No. 60325205, the National Natural Science Foundation of China under Grant No. 60673146, the National High Technology Development 863 Program of China under Grants No. 2002AAl10010, No. 2005AAl10010, No. 2005AAl19020, and the National Grand Fundamental Research 973 Program of China under Grant No. 2005CB321600.
关键词:
精简指令集计算机, 分级存储器体系, 存储单元, 微处理器, general-purpose processor, superscalar pipeline, out-of-order execution, non-blocking cache, physical design,synthesis flow, bit-sliced placement, crafted cell, performance evaluation
中文摘要:
这篇论文介绍微建筑学;Godson-2E 处理器的物理实现,它是支持 64 位 MIPS 指令表的四问题的超标量 RISC。好攻击的打乱次序的实行的采纳;存储器层次技术帮助 Godson-2E 完成高效。Godson-2E 处理器身体上与某切小点的用手的放置用基于房间的方法论在 7 金属 90nm CMOS 工艺被设计了;很多个精心制作的房间;宏。处理器能在 1GHz 被运用;比 500 高完成说明 CPU2000 率。
英文摘要:
This paper introduces the microarchitecture and physical implementation of the Godson-2E processor, which is a four-issue superscalar RISC processor that supports the 64-bit MIPS instruction set. The adoption of the aggressive out-of-order execution and memory hierarchy techniques help Godson-2E to achieve high performance. The Godson-2E processor has been physically designed in a 7-metal 90nm CMOS process using the cell-based methodology with some bitsliced manual placement and a number of crafted cells and macros. The processor can be run at 1GHz and achieves a SPEC CPU2000 rate higher than 500.