在复杂的电磁环境下,GPS接收机跟踪环容易受到外界的干扰而发生失锁,从而无法正常进行导航电文的解调和定位解算。本文定量分析了外界干扰对GPS接收机跟踪环路性能的影响。在给出了载波跟踪环和C/A码跟踪环测量误差的基础上,研究了环路参数与载噪比跟踪门限之间的关系;通过建立干扰信号链路模型,定量分析了不同类型的干扰功率对跟踪环的有效干扰范围。基于FPGA开发平台的验证结果表明,通过使热噪声颤动和动态应力误差之和达到最小以获得最优环路带宽,可有效地改善GPS接收机跟踪环的测量精度,从而最大程度地提高跟踪环的抗干扰能力。
The tracking loops of GPS receivers are easy to lose lock due to outside interference in complex electromagnetic environments, which causes the GPS receivers fail to demodulate the navigation messages and do positioning calculations. The influence of external interference on GPS receiver tracking loop performance is analyzed quantitatively. On the basis of measuring errors of the carrier tracking loop and the C/A code tracking loop, the relation between carrier-to-noise power density ratio and loop parameters is researched. Using the interference signal link model established in this paper, the effective interferential range of various jamming power on tracking loops is studied quantitatively. The simulation results based on FPGA development platform indicate that the optimal loop bandwidth can be obtained by minimizing the sum of thermal noise vibration and dynamic stress error and it can improve the measurement accu- racy and enhance the anti-interference ability.