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一种共游程码的测试数据压缩方案
  • 期刊名称:《计算机研究与发展》, 45(10):1646-1653, 2008 年10 月
  • 时间:0
  • 分类:TP306.2[自动化与计算机技术—计算机系统结构;自动化与计算机技术—计算机科学与技术]
  • 作者机构:[1]合肥工业大学计算机与信息学院,合肥230009, [2]安庆师范学院教育科学与技术系,安徽安庆246011
  • 相关基金:国家自然科学基金重大研究计划基金项目(90407008);国家自然科学基金重点项目(60633060);安徽省教育厅自然科学基金项目(KJ2008B031)
  • 相关项目:数字VLSI电路测试技术研究
中文摘要:

提出了一种新的基于游程编码的测试数据压缩/解压缩的算法:共游程码(SRLCS)编码,它在使用较短的代码字来代替较长的游程的传统游程编码基础上,进一步充分利用了相邻游程之间的相关性,使用一位来代替与前一游程相同的整个后一游程,这样整个后一游程可以用一位来表示,达到从多位到一位的转换,进一步压缩了测试数据.由于测试数据中存在大量的无关位,对无关位适当的赋值,可以增加连续游程长度相同的概率,提出了一种针对共游程码的无关位填充算法.理论分析和实验结果证明该方案具有高数据压缩率、硬件实现简单等特点.

英文摘要:

One of the major challenges in testing integrated circuits is dealing with the large test data size. To reduce the volume of test data, several test data compression schemes have been presented. But all of these schemes do not explore the relationship between consecutive runs. So a new scheme of test data compression/decompression, namely sharing-run-length code scheme (SRLCS) is presented, which is based on run length coding. It explores further the relationship between consecutive runs on the basis of traditional run length coding characteristic which uses shorter eodeword to represent longer run length. Thus, only 1 bit needs to represent the whole later run in immediate two runs whose lengths are the same in this scheme. ATPG tools generate test patterns with many don't care bits, which are 95% to 99% of the bits in test data for large industrial circuits. So filling the don't care bits in test data appropriately can increase the probability of the consecutive runs whose lengths are the same. A strategy of filling don't care bits is also proposed for this scheme. Compared with other schemes, this scheme has some characteristics, such as high compression ratio and easy control and implementation. Theoretical analysis and experimental results for the Mintest test set of ISCAS- 89 benchmark circuits show that the proposed scheme is a very efficient compression method.

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