位置：立项数据库 > 立项详情页
射频/毫米波集成电路与无线通信系统芯片设计
  • 项目名称：射频/毫米波集成电路与无线通信系统芯片设计
  • 项目类别：优秀青年科学基金项目
  • 批准号：61222405
  • 申请代码：F040202
  • 项目来源：国家自然科学基金
  • 研究期限：2013-01-01-2015-12-31
  • 项目负责人：池保勇
  • 负责人职称：副研究员
  • 依托单位：清华大学
  • 批准年度：2012
中文摘要：

随着集成电路的发展，芯片上或芯片与芯片之间的数据交互越来越频繁，互连成为限制复杂SoC或电子系统性能的瓶颈。采用60GHz毫米波频段实现的射频互连具有数据传输率高、定向传输性好、体积小、>mm的通信距离及电磁兼容性好等优点，成为一种新型高数据率互连方式。本项目围绕CMOS 工艺下超高数据率近距离互连毫米波通信芯片中的关键共性技术问题进行研究，包括探讨便于集成的超高数据率毫米波集成通信芯片的系统架构，研究超宽带(>10GHz)毫米波前端电路的实现和优化方法，探讨便于实现的、可支持超高数据率（>10Gbps）的调制解调方式及模拟域实现方法，最后基于65nm CMOS工艺实现60GHz超高数据率近距离互连的毫米波通信芯片，并实现芯片与芯片之间的超高速射频互连的演示系统。该项目致力于解决CMOS工艺下超高数据率近距离互连毫米波通信芯片中的关键共性技术问题，为我国开展毫米波互连技术的开发奠定基础。

中文主题词： 毫米波集成电路；无线收发机；宽带放大器；通信系统芯片；QPSK调制/解调器
结论摘要：

英文主题词Mm-Wave Integrated Circuits；Wireless Transceiver；Wide-Band Amplifier；Communication Chip；QPSK Modulator/Demodulator

成果综合统计
成果类型
数量
  • 期刊论文
  • 会议论文
  • 专利
  • 获奖
  • 著作
  • 30
  • 24
  • 0
  • 0
  • 0
期刊论文
An Efficiency-Enhanced Stacked 2.4-GHz CMOS Power Amplifier With Mode Switching Scheme for WLAN Appl
A 0.1–6.0-GHz Dual-Path SDR Transmitter Supporting Intraband Carrier Aggregation in 65-nm CMOS
Research on CMOS Mm-Wave Circuits and Systems for Wireless Communications
A 0.1-6.0-GHz Dual-Path SDR Transmitter Supporting Intraband Carrier Aggregation in 65-nm CMOS
An LP/CBP reconfigurable analog baseband circuit for software-defined radio receivers in 65 nm CMOS
A 0.1-4 GHz SDR receiver with reconfigurable 10-100 MHz signal bandwidth in 65 nm CMOS
142 GHz amplifier with 18.5 dB gain and 7.9 mW DC power in 65 nm CMOS
A fully-differential phase-locked loop frequency synthesizer for 60-GHz wireless communication
An 110 GHz CMOS Colpitts VCO based on switched coupled-inductor
A 180 GHz differential Colpitts VCO in 65 nm CMOS
A W-Band Injection-LockedFrequency Doulber Based on Top-Injected Coupled Resonator
A 47.6-71.0-GHz 65-nm CMOS VCO based on magnetically coupled π-type LC network
A 60-GHz CMOS Dual-Mode Power Amplifier with Efficiency Enhancement at Low Output Power
A 5/20MHz BW Reconfigurable Quadrature Bandpass CT Sigma-Delta Modulator with Anti-pole-splitting Op
A 0.1-1.5 GHz Harmonic Rejection Receiver Front-End With Phase Ambiguity Correction, Vector Gain Cal
An inductorless CMOS programmable-gain amplifier with a>3 GHz bandwidth for60 GHz wireless transc
Co-Design of 60-GHz Wideband Front-End IC With On-Chip T/R Switch Based on Passive Macro-Modeling
A W-Band Power Amplifier Utilizing a Miniaturized Marchand Balun Combiner
An inductorless CMOS programmable-gain amplifier with a 〉 3 GHz bandwidth for 60 GHz wireless transceivers
会议论文
An 8.2 GHz Triple CouplingLow-Phase-Noise Class-F QVCO in 65nm CMOS
A Sub-GHz Low-Power Transceiver with PAPR-Tolerant Power Amplifier for 802.11ah Applications
A Fully-Integrated Reconfigurable Transceiver for Narrowband Wireless Communication in 180nm CMOS
A 0.5-30GHz Wideband Differential CMOS T/RSwitch with Independent Bias and LeakageCancellation Techn
A half rate CDR with DCD cleaning up and quadrature clock calibration for 20Gbps 60GHz communication
Co-design of 60GHz wideband front-end IC with on-chip Tx/Rx switch based on passive macro-modeling
An 180nm Fully-Integrated Dual-Channel Reconfigurable Receiver For GNSS Interoperations
An Asymmetric Dual-Channel Reconfigurable Receiver for GNSS in 180nm CMOS
A Self-Healing mm-Wave Amplifier Using Digital Controlled Artificial Dielectric Transmission Lines
A Resonant-Mode Switchable VCO with 47.6-71.0 GHz Tuning Range Based on p-Type LC Network
A 60-GHz WirelessTransceiver with Dual-Mode Power Amplifier for IEEE 802.11ad in 65nm CMOS
A half rate CDR with DCD cleaning up and quadrature clock calibration for 20Gbps 60GHz communication
An Integrated 60GHz 5Gb/s QPSK Transmitter with On-Chip T/R Switch and Fully-Differential PLL Freque
A Frequency DoublingTwo-Path Phased-Array FMCW Radar Transceiver in 65nm CMOS
A Multi-mode ReconfigurableLowpass/Complex Bandpass CT Sigma-Delta Modulator for Short Range Wireles
A 0.1-1.5G SDR Transmitterwith Two-Stage Harmonic Rejection Power Mixer in 65-nm CMOS
A 0.1-5.0GHz Self-Calibrated SDR Transmitter with -62.6dBc CIM3 in 65nm CMOS
An Efficiency-Enhanced 2.4GHz Stacked CMOS Power Amplifier with Mode Switching Scheme for WLAN Appli
A 54.4-mW 4th-order Quadrature Bandpass CT ΣΔ Modulator with 33-MHz BW and 10-bit ENOB for a GNSS re
Co-design of 60GHz wideband front-end IC with on-chip Tx/Rx switch based on passive macro-modeling
A Reconfigurable AnalogBaseband for Low-Power Wi-Fi Receiver
A 100M-1.5 GHzHarmonic-Rejection SDR Receiver Front-End
A 0.1-5GHz SDR Transmitter with Dual-Mode Power Amplifier and Digital-Assisted I/Q Imbalance Calibra
A 5/20MHz-BW 4.2/8.1mW CT QBP Delta-Sigma Modulator with Digital I/Q Calibration for GNSS Receivers
池保勇的项目
深亚微米工艺下SOC中射频IP模块实现的基础问题研究
期刊论文 25 会议论文 11
射频集成电路的在片自校准关键技术的研究
期刊论文 14 会议论文 7 专利 5
CMOS工艺下毫米波雷达关键电路技术研究
期刊论文 10 会议论文 13 专利 3
基于纳米磁性材料的混合型超微集成磁性电感的研究及其在CMOS 超宽带射频集成电路系统芯片中的应用
期刊论文 54 会议论文 19
数字密集型超高速毫米波通信集成电路关键技术研究