欢迎您!
东篱公司
退出
申报数据库
申报指南
立项数据库
成果数据库
期刊论文
会议论文
著 作
专 利
项目获奖数据库
位置:
成果数据库
>
会议
> 会议详情页
FPGA Implementation of a Scheduler Supporting Parallel Dataflow Execution
所属机构名称:中国科学技术大学苏州研究院
会议名称:2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)
时间:2013.5.19
成果类型:会议
相关项目:面向服务的异构多核可重构片上系统任务自动并行化机制研究
同会议论文项目
面向服务的异构多核可重构片上系统任务自动并行化机制研究
期刊论文 27
会议论文 27
同项目会议论文
SOBA: A Services-Oriented Browser Architecture with Distributed URL-Filtering Mechanisms for Teenage
Big Data Genome Sequencing on Zynq based Clusters
Co-processing with Dynamic Reconfiguration on Heterogeneous MPSoC: Practices and Design Tradeoffs
A FPGA-based high performance acceleration platform for the Next Generation long read mapping
Static or Dynamic: Trade-offs for Task Dependency Analysis
Automatic Loop-based Pipeline Optimization on Reconfigurable Platform
Parallel Dataflow Execution for Sequential Programs on Reconfigurable Hybrid MPSoCs
A TASK-LEVEL OOO FRAMEWORK FOR HETEROGENEOUS SYSTEMS
A Deep Learning accelerator based FPGA
An FPGA-Based Accelerator for Neighborhood-Based Collaborative Filtering Recommendation Algorithms
SAKMA: Specialized FPGA-Based AcceleratorArchitecture for Data-IntensiveK-Means Algorithms
An Intelligent Transportation System using RFID based Sensors
Instruction Extension and Generation for Adaptive Processors
SmartClass: A Services-Oriented Approach for University Resource Scheduling
SmartMal: A Service-oriented Behavioral Malware Detection Framework for Smartphones
Detecting Associations in Large Dataset on MapReduce
Pipeline Optimization for Loops on Reconfigurable Platform
A FPGA-based high performance acceleration platform for the Next Generation long read mapping
Coordinate page allocation and thread group for improving main memory power efficiency
Coordinate Task and Memory Management for Improving Power Efficiency
Kernel-User Space Separation in DRAM Memory
Multi-objective aware design flow for coarse-grained systems on chip
Memory Power Optimization on Different Memory Address Mapping Schemas
SODA: Software Defined FPGA based Accelerators for Big Data
Trade-offs between the Sensitivity and the Speed of the FPGA-based Sequence Aligner
An Intelligent Transportation System using RFID based Sensors