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面向服务的异构多核可重构片上系统任务自动并行化机制研究
  • 项目名称：面向服务的异构多核可重构片上系统任务自动并行化机制研究
  • 项目类别：青年科学基金项目
  • 批准号：61202053
  • 申请代码：F020308
  • 项目来源：国家自然科学基金
  • 研究期限：2013-01-01-2015-12-31
  • 项目负责人：王超
  • 依托单位：中国科学技术大学苏州研究院
  • 批准年度：2012
中文摘要：

将异构多核片上系统与可重构技术相结合是嵌入式计算系统的发展趋势之一。然而，编程墙问题和任务自动并行化问题给异构多核可重构片上系统的发展带来了巨大的挑战。为了解决这两个问题，我们首次将面向服务思想引入异构多核可重构片上系统，拟构建面向服务的中间件框架，将异构计算资源抽象为服务体，将软硬件计算功能定义为服务，为用户提供一致的编程模型，以此解决编程墙问题。在此基础上，为了提升任务的并行度，本项目重点研究任务自动化并行机制中的软硬件功能动态划分策略和支持乱序执行的动态调度算法，拟在任务划分算法设计中同时考虑热点任务、软硬件差异以及可重构特性等因素，并将指令级的重命名技术扩展到任务级，提出一种新颖的调度算法来支持任务的乱序执行。本课题的顺利开展对解决异构多核可重构片上系统的编程墙问题提供了新方法和新思路，同时对任务的自动并行化研究具有重要理论意义和应用价值。

中文主题词： 可重构计算；面向服务；自动并行化；任务调度；资源管理
结论摘要：

英文主题词Reconfigurable Computing；Services-Oriented Architecture；Automatic Parallelization；Task Scheduling；Resources Management

成果综合统计
成果类型
数量
  • 期刊论文
  • 会议论文
  • 专利
  • 获奖
  • 著作
  • 27
  • 27
  • 0
  • 0
  • 0
期刊论文
Codem: A Software/Hardware Codesign Flow for Embedded Multicore Systems Supporting Hardware Services
Memory Power Optimization on Low-bit Multi-access Cross Memory Address Mapping Schema
A star network approach in heterogeneous multiprocessors system on chip
MP-Tomasulo: a Dependency-aware Automatic Parallel Execution Engine for Sequential Programs
Colored Petri Net Model with Automatic Parallelization on Real-Time Multicore Architectures
Definitions of predictability for Cyber Physical Systems
Soft computing in big data intelligent transportation systems
Evaluation and Tradeoffs for Out-of-Order Execution on Reconfigurable Heterogeneous MPSoC
Services-oriented URL Filtering and Verification
Fast Approximate Hash Table Using Extended Counting Bloom Filter
Amdahl’s and Hill-Marty Laws Revisited for FPGA based MPSoCs: from Theory to Practice
Heterogeneous Cloud Framework for Big Data Genome Sequencing
Accelerating the Next Generation long read mapping with the FPGA-based system
A Case Study of Parallel JPEG Encoding on an FPGA
CRAIS: A Crossbar based Interconnection Scheme on FPGA for Big Data
A Service-oriented Behavioral Malware Detection Framework for Android based Smartphones
Heterothread: Hybrid Thread Level Parallelism on Heterogeneous Multicore Architectures
Hardware Implementation on FPGA for Task-level Parallel Dataflow Execution Engine
A Classroom Scheduling Service for Smart Classes
一个平衡功耗、性能和公平性的组管理方法
支持动态部分重构特性的异构多核体系结构
一种基于顶点位置树的可重构软硬件迭代协同算法
基于有色Petri网的多处理器片上系统调度方法
交互式系统下基于任务重要性的DVFS技术
基于I/O空闲率的硬盘功耗建模与评估方法研究
一种运用块级局部性的闪存缓存管理策略
会议论文
SOBA: A Services-Oriented Browser Architecture with Distributed URL-Filtering Mechanisms for Teenage
Big Data Genome Sequencing on Zynq based Clusters
Co-processing with Dynamic Reconfiguration on Heterogeneous MPSoC: Practices and Design Tradeoffs
A FPGA-based high performance acceleration platform for the Next Generation long read mapping
Static or Dynamic: Trade-offs for Task Dependency Analysis
Automatic Loop-based Pipeline Optimization on Reconfigurable Platform
Parallel Dataflow Execution for Sequential Programs on Reconfigurable Hybrid MPSoCs
A TASK-LEVEL OOO FRAMEWORK FOR HETEROGENEOUS SYSTEMS
A Deep Learning accelerator based FPGA
An FPGA-Based Accelerator for Neighborhood-Based Collaborative Filtering Recommendation Algorithms
SAKMA: Specialized FPGA-Based AcceleratorArchitecture for Data-IntensiveK-Means Algorithms
An Intelligent Transportation System using RFID based Sensors
Instruction Extension and Generation for Adaptive Processors
SmartClass: A Services-Oriented Approach for University Resource Scheduling
SmartMal: A Service-oriented Behavioral Malware Detection Framework for Smartphones
Detecting Associations in Large Dataset on MapReduce
FPGA Implementation of a Scheduler Supporting Parallel Dataflow Execution
Pipeline Optimization for Loops on Reconfigurable Platform
A FPGA-based high performance acceleration platform for the Next Generation long read mapping
Coordinate page allocation and thread group for improving main memory power efficiency
Coordinate Task and Memory Management for Improving Power Efficiency
Kernel-User Space Separation in DRAM Memory
Multi-objective aware design flow for coarse-grained systems on chip
Memory Power Optimization on Different Memory Address Mapping Schemas
SODA: Software Defined FPGA based Accelerators for Big Data
Trade-offs between the Sensitivity and the Speed of the FPGA-based Sequence Aligner
An Intelligent Transportation System using RFID based Sensors
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