位置：成果数据库 > 会议 > 会议详情页
Experiment and Simulation of Transistor Level Fault model of IDDT Test
  • 所属机构名称：电子科技大学
  • 会议名称：2009 IEEE International Conference on Applied Superconductivity and Electromagnetic Devices(ASEMD)
  • 成果类型：会议
  • 相关项目：片上网络（NoC）的时延与串扰测试方法及可测试性设计模型
作者： Shuyan Jiang|
同会议论文项目
片上网络（NoC）的时延与串扰测试方法及可测试性设计模型
期刊论文 12 会议论文 8 专利 2
同项目会议论文
Development of driving program of wiring harness based on S3c44bo
Test Control&Communication of Hierarchical Design-For-Testability
Experiment and Simulation of Transistor Level Fault model of IDDT Test
Experiment and Simulation of Transistor Level Fault model of IDDT Test
A Test Method of Interconnection online Detection of NoC Based on 2D Torus Topology
Fault Tolerance with Dual Module Redundancy for Dynamic Reconfigurable FPGAs
Experiment and Simulation of Transistor Level Fault model of IDDT Test