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Adaptive Diagnostic Pattern Generation for Scan Chains
  • 所属机构名称：中国科学院计算技术研究所
  • 成果类型：会议
  • 相关项目：数字VLSI电路测试技术研究
同会议论文项目
数字VLSI电路测试技术研究
期刊论文 158 会议论文 59 著作 2
同项目会议论文
P2CLRAF: An Pre-and Post-silicon Cooperated Circuit Lifetime Reliability Analysis Framework
An On-Chip Clock Generation Scheme for Faster than-at-Speed Delay Testing
An Abstraction-Guided Simulation Approach using Markov Models for Microprocessor Verification
IVF: Characterizing the Vulnerability of Microprocessor Structures to Intermittent Faults
Performance-Asymmetry-Aware Topology Virtualization for Defect-tolerant NoC-based Many-core Processo
Impact-Factor-Guided X-Filling for Peak Power Reduction during Test
A Resilient On-chip Router Design Through Data Path Salvaging
On Reducing Both Shift and Capture Power for Scan-Based Testing
A New Multiple-Round DOR Routing for 2D NoC Meshes
A New Post-Silicon Debug Approach Based on Suspect Window
A scan-based delay test method for reduction of overtesting
An Efficient Algorithm for Finding a Universal Set of Testable Long Paths
Codeword Selection for Crosstalk Avioidance and Error Correction on Interconnects
Robust Test Generation for Power Supply Noise induced Path Delay Faults
Automatic selection of internal observation signals for design verification
Flip-flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan
Diagnosis of Multiple Arbitrary Faults with Mask and Reinforcement Effect
Frequency Analysis Method for Propagation of Transient Errors in Combinational Logic
On Selection of Testable Paths with Specified Lengths for Faster- Than- At-Speed Testing
Address Remapping for Static NUCA in NoC-based Degradable Chip-Multiprocessors
An On-Chip Test Clock Contrl Scheme for Multi-Clock At-Speed Testing
Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis
A Low Overhead On-chip Path Delay Measurement Circuit
Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power
A unified online Fault Detection scheme via checking of Stability Violation
On Capture Power-Aware Test Data Compression for Scan-Based Testing
The Design-for-Testability Features of A Godson Purpose Microprocessor
Static Crosstalk Noise Analysis with Transition Map
Test Cost Efficiency Exploration for CMT Processors
A Routing Algorithm for Random Error Tolerance in Network-on-chip
Localized Rand Access Scan: Towards Low Area and Routing Overhead
A Case Study on At-Speed Testing for A Gigahertz Microprocessor
A new radiation hardened by design latch for Ultra-Deep-Sub-Micron Technologies
A Design- for-Diagnosis Technique for Diagnosing Combinational Circuit Faults with Faulty Scan Chain
Accelerating Lightpath Setup Via Broadcasting in Binary-Tree Waveguide in Optical NoCs
Test Pattern Selection for Small-Delay Defects Considering Hazards
Multiple Coupling Effects Oriented Path Delay Test Generation
T2-TAM：Reusing Infrastructure Resource to Provide Parallel Testing for NoC based Chip
Variation-Aware Scheduling for Chip Multiprocessor with Thread-Level Redundancy
On Generation of a Universal Path Candidate Set Containing Testable Long Paths
Test Generation for Crosstalk Glitches Considering?Multiple Coupling Effects
M-IVC: Using Multiple Input Vectors to Minimize Aging-induced Delay
A novel collaborative scheme of test data compression based on fixed-plus-variable-length coding
Reliable Network-on-Chip Router for Crosstalk and Soft Error Tolerance
Accelerating Strategy For Functional Test of NoC Communication Fabric
Diagnosis of Mask-Effect Multiple Timing Faults in Scan Chains
Leveraging the Core-Level Complementary Effects of PVT Variations to Reduce Timing Emergencies in Mu
Fast Path Selection for Testing of Small Delay Defects Considering Path Correlations
nGFSIM: A GPU-Based 1-to-n-Detection Fault Simulator and its Applications
MicroFix: Exploiting Path-grained Timing Adaptability for Improving Power-Performance Efficiency
Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction
Vertical Interconnects Squeezing in Symmetric 3D Mesh Network-on-Chip
Graph Partition based Path Selection for Testing of Small Delay Defects
Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects
Online Computing and Predicting Architectural Vulnerability Factor of Microprocessor Structures
Substantial Fault Pairs at-A-Time (SFPAT): An Automatic Diagnostic Pattern Generation Method
Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topolog
iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-B