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A Time-to-Digital Converter Based AFC for Wideband Frequency Synthesizer
  • 所属机构名称：复旦大学
  • 会议名称：The 2012 IEEE International Symposium on Circuits and Systems
  • 时间：2012.5.20
  • 成果类型：会议
  • 相关项目：基于全数字锁相环和多模无线应用的频率综合器研究
作者： Jin Zhou|Ning Li|Junyan Ren|Jinghong Chen|
同会议论文项目
基于全数字锁相环和多模无线应用的频率综合器研究
期刊论文 16 会议论文 28
同项目会议论文
A 30.4% tuning range Quadrature LC VCO using Class-C structure
A DC-12.8GHz Fully Differential Buffer with 0.35dB Gain Variation for Ultra-Wideband Applications
A 5.6~8.2GHz QVCO with a New DCCA Circuit
A 0.3~17.2GHz Frequency Divider with Capacitive Degeneration In 130nm CMOS,
A DC-12.8GHz Fully Differential Buffer with 0.35dB Gain Variation for Ultra-Wideband Applications
A 1.5 mW 26.2–32.2 GHz Divide-by-4 Injection-Locked Frequency Divider in 130 nm CMOS Process
A High-resolution, High-linearity, Two-step Time-to-Digital Converter for Wideband Counter-assisted
Design of a LC VCO and injection locked frequency divider special for Ka-band application
A High-resolution, High-linearity, Two-step Time-to-Digital Converter for Wideband Counter-assisted
Design of a LC VCO and injection locked frequency divider special for Ka-band application
A 5.6~8.2GHz QVCO with a New DCCA Circuit
A 0.3~17.2GHz Frequency Divider with Capacitive Degeneration In 130nm CMOS,
Algorithms Based on All-Digital Phase-Locked Loop for Fast-lockingand Spur Free
A High-resolution, High-linearity, Two-step Time-to-Digital Converter for Wideband Counter-assisted
Design of a LC VCO and injection locked frequency divider special for Ka-band application
A 5.6~8.2GHz QVCO with a New DCCA Circuit
A 0.3~17.2GHz Frequency Divider with Capacitive Degeneration In 130nm CMOS,
A DC-12.8GHz Fully Differential Buffer with 0.35dB Gain Variation for Ultra-Wideband Applications
A 1.5 mW 26.2–32.2 GHz Divide-by-4 Injection-Locked Frequency Divider in 130 nm CMOS Process
A DC-12.8GHz Fully Differential Buffer with 0.35dB Gain Variation for Ultra-Wideband Applications
A 1.5 mW 26.2–32.2 GHz Divide-by-4 Injection-Locked Frequency Divider in 130 nm CMOS Process
A High-resolution, High-linearity, Two-step Time-to-Digital Converter for Wideband Counter-assisted
Design of a LC VCO and injection locked frequency divider special for Ka-band application
A 5.6~8.2GHz QVCO with a New DCCA Circuit
A 0.3~17.2GHz Frequency Divider with Capacitive Degeneration In 130nm CMOS,
A DC-12.8GHz Fully Differential Buffer with 0.35dB Gain Variation for Ultra-Wideband Applications
A 1.5 mW 26.2–32.2 GHz Divide-by-4 Injection-Locked Frequency Divider in 130 nm CMOS Process