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On Predicting the Maximum Circuit Aging
所属机构名称:中国科学院计算技术研究所
会议名称:IEEE Workshop on RTL and High Level Test (WRTLT)
成果类型:会议
相关项目:片上网络芯片中路由器电路和互连线的测试方法研究
作者:
李晓维|李华伟|韩银和|张磊|靳松|
同会议论文项目
片上网络芯片中路由器电路和互连线的测试方法研究
期刊论文 13
会议论文 22
专利 3
同项目会议论文
nGFSIM : A GPU-Based Fault Simulator for 1-to-n Detection and its Applications
Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy
Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power
Scan Slices Compression Technique Using Dynamical Updating Reference Slices
M-IVC: Using Multiple Input Vectors to Minimize Aging-induced Delay
A New Post-silicon Debug Approach Based on Suspect Window
Vertical Interconnects Squeezing in Symmetric 3D Mesh Network-on-Chip
A Resilient On-chip Router Design Through Data Path Salvaging
An Abacus Turn Model for Time/Space-Efficient Reconfigurable Routing
A New Multiple-Round DOR Routing for 2D Network-on-chip Meshes
MicroFix: Exploiting Path-grained Timing Adaptability for Improving Power-Performance Efficiency
A Unified Online Fault Detection Scheme via Checking of Stability Violation
A Fast and Memory-Efficient Fault Simulation Using GPU
Wear Rate Leveling: Lifetime Enhancement of PRAM with Endurance Variation
Avoiding Data Repetition and Data Loss in Debugging Multiple-Clock Chips
FlexMemory: exploiting and managing abundant off-chip optical bandwidth
P2CLRAF: An Pre- and Post-silicon Cooperated Circuit Lifetime Reliability Analysis Framework
Performance-Asymmetry-Aware Topology Virtualization for Defect-tolerant NoC-based Many-core Processo
Address Remapping for Static NUCA in NoC-based Degradable Chip-Multiprocessors
Accelerating Lightpath Setup Via Broadcasting in Binary-Tree Waveguide in Optical NoCs
Leveraging the Core-Level Complementary Effects of PVT Variations to Reduce Timing Emergencies in Mu